Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

1.9. Recommended Speed Grades

Table 7.   Cyclone V Recommended Speed Grades for Link Widths and Application Layer Clock Frequencies Intel recommends setting the Quartus® Prime Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus® Prime Help. For more information about how to effect the Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus® Prime Handbook. .

Cyclone V Gen2 variants must use GT parts.

Link Rate

Link Width

Interface Width

Application Clock Frequency (MHz)

Recommended Speed Grades

Gen1

×1

64 bits

62.5 2,125

–6, –7,–8

×2

64 bits

125

–6, –7,–8

×4

64 bits

125

–6, –7,–8

Gen2

×1

64 bits

125

–7

×2

64 bits

125

–7

×4

128 bits

125

–7

2 This is a power-saving mode of operation

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