1. Datasheet 2. Getting Started with the Avalon‑MM Cyclone V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Design Implementation 9. Additional Features 10. Transceiver PHY IP Reconfiguration 11. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
184.108.40.206. Avalon-MM to PCI Express Interrupt Status Registers 220.127.116.11. Avalon-MM to PCI Express Interrupt Enable Registers 18.104.22.168. PCI Express Mailbox Registers 22.214.171.124. Avalon-MM-to-PCI Express Address Translation Table 126.96.36.199. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 188.8.131.52. Avalon-MM Mailbox Registers 184.108.40.206. Control Register Access (CRA) Avalon-MM Slave Port
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
The Hard IP for PCI Express offers the following interrupt mechanisms:
- Message Signaled Interrupts (MSI)— MSI uses the TLP single dword memory writes to to implement interrupts. This interrupt mechanism conserves pins because it does not use separate wires for interrupts. In addition, the single dword provides flexibility in data presented in the interrupt message. The MSI Capability structure is stored in the Configuration Space and is programmed using Configuration Space accesses.
- MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. The MSI-X Capability structure points to an MSI-X table structure and MSI-X PBA structure which are stored in memory. This scheme is in contrast to the MSI capability structure, which contains all of the control and status information for the interrupt vectors.
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