Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

3.9. Avalon Memory‑Mapped System Settings

Table 17.  Avalon Memory-Mapped System Settings
Parameter Value Description
Avalon-MM data width

64-bit

128-bit

Specifies the data width for the Application Layer to Transaction Layer interface. Refer to Application Layer Clock Frequencies for All Combinations of Link Width, Data Rate and Application Layer Interface Widths for all legal combinations of data width, number of lanes, Application Layer clock frequency, and data rate.
Avalon-MM address width

32-bit

64-bit

Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain. When you select 32-bit addresses, the PCI Express Avalon-MM Bridge performs address translation. When you specify 64-bits addresses, no address translation is performed in either direction. The destination address specified is forwarded to the Avalon-MM interface without any changes.

For the Avalon-MM interface with DMA, this value must be set to 64.

Peripheral mode

Requester/Completer

Completer-Only

Specifies whether the Avalon‑MM Cyclone V Hard IP for PCI Express is capable of sending requests to the upstream PCI Express devices, and whether the incoming requests are pipelined.

Requester/Completer—In this mode, the Hard IP can send request packets on the PCI Express TX link and receive request packets on the PCI Express RX link.

Completer-Only—In this mode, the Hard IP can receive requests, but cannot initiate upstream requests. However, it can transmit completion packets on the PCI Express TX link. This mode removes the Avalon-MM TX slave port and thereby reduces logic utilization.

Single DW Completer On/Off

This is a non‑pipelined version of Completer Only mode. At any time, only a single request can be outstanding. Single DWORD completer uses fewer resources than Completer Only. This variant is targeted for systems that require simple read and write register accesses from a host CPU. If you select this option, the width of the data for RXM BAR masters is always 32 bits, regardless of the Avalon-MM width.

For the Avalon-MM interface with DMA, this value must be Off .

Control register access (CRA) Avalon-MM slave port On/Off

Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port. This option is required for Requester/Completer variants and optional for Completer Only variants. Enabling this option allows read and write access to bridge registers, except in the Completer‑Only single DWORD variations.

Enable multiple MSI/MSI-X support On/Off

When you turn this option On, the core exports top‑level MSI and MSI‑X interfaces that you can use to implement a Customer Interrupt Handler for MSI and MSI‑X interrupts. For more information about the Custom Interrupt Handler, refer to Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI‑X Support. If you turn this option Off, the core handles interrupts internally.

Auto enabled PCIe interrupt (enabled at power-on) On/Off

Turning on this option enables the Avalon‑MM Cyclone V Hard IP for PCI Express interrupt register at power‑up. Turning off this option disables the interrupt register at power‑up. The setting does not affect run‑time configuration of the interrupt enable register.

For the Avalon-MM interface with DMA, this value must be Off.

Enable hard IP status bus On/Off When you turn this option on, your top-level variant includes the signals necessary to connect to the Transceiver Reconfiguration Controller IP Core, your variant, including:
  • Link status signals
  • ECC error signals
  • TX and RX parity error signals
  • Completion header and data signals, indicating the total number of Completion TLPs currently stored in the RX buffer
Intel recommends that you include the Transceiver Reconfiguration Controller IP Core in your design to improve signal quality.
Enable hard IP status extension bus On/Off When you turn this option on, your top-level variant includes signals that are useful for debugging, including link training and status, error, and the Transaction Layer Configuration Space signals. The top-level variant also includes signals showing the start and end of packets, error, ready, and BAR signals for the native Avalon-ST interface that connects to the Transaction Layer. The following signals are included in the top-level variant:
  • Link status signals
  • ECC error signals
  • Transaction Layer Configuration Space signals
  • Avalon-ST packet, error, ready, and BAR signals
Avalon to PCIe Address Translation Settings
Number of address pages 1, 2, 4, 8, 16, 32,

64, 128, 256, 512

Specifies the number of pages required to translate Avalon-MM addresses to PCI Express addresses before a request packet is sent to the Transaction Layer. Each of the 512 possible entries corresponds to a base address of the PCI Express memory segment of a specific size. This parameter is only necessary when you select 32-bit addressing.

Size of address pages 4 KBytes4 GBytes

Specifies the size of each memory segment. Each memory segment must be the same size. Refer to Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Bridge for more information about address translation. This parameter is only necessary when you select 32-bit addressing.

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