Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

2. Getting Started with the Avalon‑MM Cyclone V Hard IP for PCI Express

You can download a design example for the Avalon‑MM Cyclone V Hard IP for PCI Express from the <install_dir>/ip/altera/altera_pcie/altera_pcie-<dev>_hip_avmm/example_designs directory. This walkthrough uses the a Gen1 x4 Endpoint, ep_g1x4.qsys.

The design examples contain the following components:

  • Avalon‑MM Cyclone V Hard IP for PCI Express IP core
  • On-Chip memory
  • DMA controller
  • Transceiver Reconfiguration Controller
  • Two Avalon-MM pipeline bridges
Figure 4. Qsys Generated Endpoint

The design example transfers data between an on‑chip memory buffer located on the Avalon-MM side and a PCI Express memory buffer located on the root complex side. The data transfer uses the DMA component which is programmed by the PCI Express software application running on the Root Complex processor.

The example design also includes the Transceiver Reconfiguration Controller which allows you to dynamically reconfigure transceiver settings. This component is necessary for high performance transceiver designs.

Note: This Getting Started chapter shows you how to create all the files for simulation and synthesis. However, this design example does not generate all the files necessary to download the design example to hardware. Refer to AN456 PCI Express High Performance Reference Design for a design that includes all files necessary to download your design to an Cyclone V FPGA Development Kit.

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