Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

7.1. Physical Layer Errors

Table 66.  Errors Detected by the Physical Layer The following table describes errors detected by the Physical Layer. Physical Layer error reporting is optional in the PCI Express Base Specification.

Error

Type

Description

Receive port error

Correctable

This error has the following 3 potential causes:

  • Physical coding sublayer error when a lane is in L0 state. These errors are reported to the Hard IP block via the per lane PIPE interface input receive status signals, rxstatus<lane_number>[2:0] using the following encodings:
    • 3'b100: 8B/10B Decode Error
    • 3'b101: Elastic Buffer Overflow
    • 3'b110: Elastic Buffer Underflow
    • 3'b111: Disparity Error
  • Deskew error caused by overflow of the multilane deskew FIFO.
  • Control symbol received in wrong lane.

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