Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

A. PCI Express Protocol Stack

The Avalon-MM Cyclone V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification. The protocol stack includes the following layers:

  • Transaction Layer—The Transaction Layer contains the Configuration Space, which manages communication with the Application Layer, the RX and TX channels, the RX buffer, and flow control credits.
  • Data Link Layer—The Data Link Layer, located between the Physical Layer and the Transaction Layer, manages packet transmission and maintains data integrity at the link level. Specifically, the Data Link Layer performs the following tasks:
    • Manages transmission and reception of Data Link Layer Packets (DLLPs)
    • Generates all transmission cyclical redundancy code (CRC) values and checks all CRCs during reception
    • Manages the retry buffer and retry mechanism according to received ACK/NAK Data Link Layer packets
    • Initializes the flow control mechanism for DLLPs and routes flow control credits to and from the Transaction Layer
  • Physical Layer—The Physical Layer initializes the speed, lane numbering, and lane width of the PCI Express link according to packets received from the link and directives received from higher layers.

The following figure provides a high‑level block diagram.

Figure 32.  Cyclone V Hard IP for PCI Express Using the Avalon-MM Interface
Table 70.  Application Layer Clock Frequencies

Lanes

Gen1

Gen2

Gen3

×1

125 MHz @ 64 bits or

62.5 MHz @ 64 bits

125 MHz @ 64 bits

125 MHz @64 bits

×2

125 MHz @ 64 bits

125 MHz @ 128 bits

250 MHz @ 64 bits or

125 MHz @ 128 bits

×4

125 MHz @ 64 bits

250 MHz @ 64 bits or

125 MHz @ 128 bits

250 MHz @ 128 bits or

125 MHz @ 256 bits

Did you find the information on this page useful?

Characters remaining:

Feedback Message