Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Document Table of Contents Channel Placement in Cyclone V Devices

Figure 18.  Cyclone V Gen1 and Gen2 Channel Placement Using the CMU PLLIn the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock.

You can assign other protocols to unused channels the if data rate and clock specification exactly match the PCIe configuration.

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