Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table

The Avalon-MM-to-PCI Express address translation table is writable using the CRA slave port. Each entry in the PCI Express address translation table is 8 bytes wide, regardless of the value in the current PCI Express address width parameter. Therefore, register addresses are always the same width, regardless of PCI Express address width.

These table entries are repeated for each address specified in the Number of address pages parameter. If Number of address pages is set to the maximum of 512, 0x1FF8 contains A2P_ADDR_SPACE511 and A2P_ADDR_MAP_LO511 and 0x1FFC contains A2P_ADDR_MAP_HI511.

Table 51.  Avalon-MM-to-PCI Express Address Translation Table, 0x1000–0x1FFF

Address

Bits

Name

Access

Description

0x1000

[1:0]

A2P_ADDR_SPACE0

RW

Address space indication for entry 0. The following encodings are defined:

  • 2’b00:. Memory Space, 32-bit PCI Express address. 32-bit header is generated. Address bits 63:32 of the translation table entries are ignored.
  • 2’b01: Memory space, 64-bit PCI Express address. 64-bit address header is generated.
  • 2’b10: Reserved
  • 2’b11: Reserved

[31:2]

A2P_ADDR_MAP_LO0

RW

Lower bits of Avalon-MM-to-PCI Express address map entry 0.

0x1004

[31:0]

A2P_ADDR_MAP_HI0

RW

Upper bits of Avalon-MM-to-PCI Express address map entry 0.

0x1008

[1:0]

A2P_ADDR_SPACE1

RW

Address space indication for entry 1. This entry is available only if the number of translation table entries (Number of address pages) is greater than 1.

The same encodings are defined for A2P_ADDR_SPACE1 as for A2P_ADDR_SPACE0.:

[31:2]

A2P_ADDR_MAP_LO1

RW

Lower bits of Avalon-MM-to-PCI Express address map entry 1.

This entry is only implemented if the number of address translation table entries is greater than 1.

0x100C

[31:0]

A2P_ADDR_MAP_HI1

RW

Upper bits of Avalon-MM-to-PCI Express address map entry 1.

This entry is only implemented if the number of address translation table entries is greater than 1.

Did you find the information on this page useful?

Characters remaining:

Feedback Message