Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers

The interrupt enable registers enable either MSI or legacy interrupts.

A PCI Express interrupt can be asserted for any of the conditions registered in the Avalon-MM to PCI Express Interrupt Status register by setting the corresponding bits in the Avalon-MM to PCI Express Interrupt Enable register.

Table 47.  Avalon-MM to PCI Express Interrupt Enable Register, 0x0050

Bits

Name

Access

Description

[31:24]

Reserved

N/A

N/A

[23:16]

A2P_MB_IRQ

RW

Enables generation of PCI Express interrupts when a specified mailbox is written to by an external Avalon‑MM master.

[15:0]

AVL_IRQ[15:0]

RW

Enables generation of PCI Express interrupts when a specified Avalon-MM interrupt signal is asserted. Your system may have as many as 16 individual input interrupt signals.

Table 48.  Avalon-MM Interrupt Vector Register - 0x0060

Bits

Name

Access

Description

[31:16]

Reserved

N/A

N/A

[15:0]

AVL_IRQ_Vector

RO

Stores the interrupt vector of the system interconnect fabric. When the host receives an interrupt, it should read this register to determine the servicing priority.

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