Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

4.6.4. PIPE Interface Signals

These PIPE signals are available for Gen1 and Gen2 variants so that you can simulate using either the serial or the PIPE interface. Simulation is much faster using the PIPE interface because the PIPE simulation bypasses the SERDES model . By default, the PIPE interface is 8 bits for Gen1 and Gen2. You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including probing these signals using SignalTap® II Embedded Logic Analyzer.

Table 32.  PIPE Interface Signals In the following table, signals that include lane number 0 also exist for other lanes.

Signal

Direction

Description

txdata0[7:0]

Output

Transmit data <n> (2 symbols on lane <n>). This bus transmits data on lane <n>.

txdatak0

Output

Transmit data control <n>. This signal serves as the control bit for txdata <n>.

txdetectrx0

Output

Transmit detect receive <n>. This signal tells the PHY layer to start a receive detection operation or to begin loopback.

txelecidle0

Output

Transmit electrical idle <n>. This signal forces the TX output to electrical idle.

txcompl0

Output

Transmit compliance <n>. This signal forces the running disparity to negative in Compliance Mode (negative COM character).

rxpolarity0

Output

Receive polarity <n>. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block.

powerdown0[1:0]

Output

Power down <n>. This signal requests the PHY to change its power state to the specified state (P0, P0s, P1, or P2).

tx_deemph0

Output

Transmit de-emphasis selection. The Cyclone V Hard IP for PCI Express sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value.

rxdata0[7:0]  (1)

Input

Receive data <n> (2 symbols on lane <n>). This bus receives data on lane <n>.

rxdatak0  (1)

Input

Receive data >n>. This bus receives data on lane <n>.

rxvalid0  (1)

Input

Receive valid <n>. This signal indicates symbol lock and valid data on rxdata <n> and rxdatak <n>.

phystatus0 (1)

Input

PHY status <n>. This signal communicates completion of several PHY requests.

eidleinfersel0[2:0]

Output

Electrical idle entry inference mechanism selection. The following encodings are defined:

  • 3'b0xx: Electrical Idle Inference not required in current LTSSM state
  • 3'b100: Absence of COM/SKP Ordered Set in the 128 us window for Gen1 or Gen2
  • 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval for Gen1 or Gen2
  • 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2
  • 3'b111: Absence of Electrical idle exit in 128 us window for Gen1

rxelecidle0 (1)

Input

Receive electrical idle <n>. When asserted, indicates detection of an electrical idle.

rxstatus0[2:0] (1)

Input

Receive status <n>. This signal encodes receive status and error codes for the receive data stream and receiver detection.

sim_pipe_ltssmstate0[4:0]

Input and Output

LTSSM state: The LTSSM state machine encoding defines the following states:

  • 5’b00000: Detect.Quiet
  • 5’b 00001: Detect.Active
  • 5’b00010: Polling.Active
  • 5’b 00011: Polling.Compliance
  • 5’b 00100: Polling.Configuration
  • 5’b00101: Polling.Speed
  • 5’b00110: config.LinkwidthsStart
  • 5’b 00111: Config.Linkaccept
  • 5’b 01000: Config.Lanenumaccept
  • 5’b01001: Config.Lanenumwait
  • 5’b01010: Config.Complete
  • 5’b 01011: Config.Idle
  • 5’b01100: Recovery.Rcvlock
  • 5’b01101: Recovery.Rcvconfig
  • 5’b01110: Recovery.Idle
  • 5’b 01111: L0
  • 5’b10000: Disable
  • 5’b10001: Loopback.Entry
  • 5’b10010: Loopback.Active
  • 5’b10011: Loopback.Exit
  • 5’b10100: Hot.Reset
  • 5’b10101: LOs
  • 5’b11001: L2.transmit.Wake
  • 5’b11010: Recovery.Speed
  • 5’b11011: Recovery.Equalization, Phase 0
  • 5’b11100: Recovery.Equalization, Phase 1
  • 5’b11101: Recovery.Equalization, Phase 2
  • 5’b11110: Recovery.Equalization, Phase 3
  • 5’b11111: Recovery.Equalization, Done
sim_pipe_rate[1:0]

Output

The 2‑bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b1X: Gen3 rate (8.0 Gbps)
sim_pipe_pclk_in

Input

This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation.

txswing0

Output

When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing.

tx_margin0[2:0]

Output

Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register. Available for simulation only.

Notes:

  1. These signals are for simulation only. For Quartus® Prime software compilation, these pipe signals can be left floating.

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