Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

C. Lane Initialization and Reversal

Connected components that include IP blocks for PCI Express need not support the same number of lanes. The ×4 variations support initialization and operation with components that have 1, 2, or 4 lanes. The ×8 variant supports initialization and operation with components that have 1, 2, 4, or 8 lanes.

Lane reversal permits the logical reversal of lane numbers for the ×1, ×2, ×4, and ×8 configurations. Lane reversal allows more flexibility in board layout, reducing the number of signals that must cross over each other when routing the PCB.

Table 77.  Lane Assignments without Lane Reversal

Lane Number

7

6

5

4

3

2

1

0

×8 IP core

7

6

5

4

3

2

1

0

×4 IP core

3

2

1

0

1 0

×1 IP core

0

Table 78.  Lane Assignments with Lane Reversal

Core Config

8

4

1

Slot Size

8

4

2

1

8

4

2

1

8

4

2

1

Lane pairings

7:0,6:1,5:2, 4:3, 3:4,2:5, 1:6,0:7

3:4,2:5,

1:6,0:7

1:6,

0:7

0:7

7:0,6:1,

5:2,4:3

3:0,2:1,

1:2,0:3

3:0,

2:1

3:0

7:0

3:0

1:0

0:0

Figure 49. Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoint on the top side of the PCB. Connecting the lanes without lane reversal creates routing problems. Using lane reversal solves the problem.

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