Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals

This optional Avalon-MM bursting slave port propagates requests from the interconnect fabric to the full-featured Avalon‑MM Cyclone V Hard IP for PCI Express. Requests from the interconnect fabric are translated into PCI Express request packets. Incoming requests can be up to 512 bytes. For better performance, Intel recommends using a read request size of 128 bytes. A 512-byte read request results in 2, 256-byte TLPs with delays until all 256 bytes are available. Performance analyses show that a 128-byte read request size results in the lowest latency for typical systems.

Table 20.  Avalon-MM TX Slave Interface Signals

Signal Name

Direction

Description

TxsChipSelect_i

Input

The system interconnect fabric asserts this signal to select the TX slave port.

TxsRead_i

Input

Read request asserted by the system interconnect fabric to request a read.

TxsWrite_i

Input

Write request asserted by the system interconnect fabric to request a write.

TxsWriteData[127 or 63:0]

Input

Write data sent by the external Avalon-MM master to the TX slave port.

TxsBurstCount[6 or 5:0]

Input

Asserted by the system interconnect fabric indicating the amount of data requested. The count unit is the amount of data that is transferred in a single cycle, that is, the width of the bus. The burst count is limited to 512 bytes.

TxsAddress_i[<w>-1:0]

Input

Address of the read or write request from the external Avalon‑MM master. This address translates to 64-bit or 32-bit PCI Express addresses based on the translation table. The <w> value is determined when the system is created.

TxsByteEnable_i[<w>-1:0]

Input

Byte enables for read and write data. A burst must be continuous. Therefore all intermediate data phases of a burst must have a byte enable value of 0xFF. The first and final data phases of a burst can have other valid values.

For the 128-bit interface, the following restrictions apply:

  • All bytes of a single dword must either be enabled or disabled.
  • If more than 1 dword is enabled, the enabled dwords must be contiguous. The following patterns are legal:
    • 16'hF000
    • 16'h0F00
    • 16'h00F0
    • 16'h000F
    • 16'hFF00
    • 16'h0FF0
    • 16'h00FF
    • 16'hFFF0
    • 16'h0FFF
    • 16'hFFFF
TxsReadDataValid_o

Output

Asserted by the bridge to indicate that read data is valid.

TxsReadData_o[127 or 63:0]

Output

The bridge returns the read data on this bus when the RX read completions for the read have been received and stored in the internal buffer.

TxsWaitrequest_o

Output

Asserted by the bridge to hold off read or write data when running out of buffer space. If this signal is asserted during an operation, the master should maintain the read or write signal and write data stable until after the wait request is deasserted. TxsRead_i must be deasserted when is > TxsWaitrequest_o asserted.

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