Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled

Application Layer logic must construct the MSI (MemWr) TLP and send it using the TX slave (TXS) interface. For designs supporting multiple MSI/MSI-X, use the signals described below. For designs using a MSI TLP, use the control register access (CRA) interface to read the MSI Capability registers. The MSI information is at address offsets 14'h3C24, 14'h3C28, 14'h3C54, and 14'h3C5C. The Bus Master Enable bit is at address 14h'3C00.

Table 24.  Exported Interrupt Signals for Endpoints when Multiple MSI/MSI‑X Support is EnabledThe following table describes the IP core’s exported interrupt signals when you turn on Enable multiple MSI/MSI-X support under the Avalon-MM System Settings banner in the parameter editor.

Signal

Direction

Description

MsiIntfc_o[81:0]

Output

This bus provides the following MSI address, data, and enabled signals:

  • MsiIntfc_o[81]: Master enable
  • MsiIntfc_o[80}: MSI enable
  • MsiIntfc_o[79:64]: MSI data
  • MsiIntfc_o[63:0]: MSI address
MsiControl_o[15:0]

Output

Provides for system software control of MSI as defined in Section 6.8.1.3 Message Control for MSI in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

  • MsiControl_o[15:9]: Reserved
  • MsiControl_o[8]: Per-vector masking capable
  • MsiControl_o[7]: 64-bit address capable
  • MsiControl_o[6:4]: Multiple Message Enable
  • MsiControl_o[3:1]: MSI Message Capable
  • MsiControl_o[0]: MSI Enable.
MsixIntfc_o[15:0]

Output

Provides for system software control of MSI-X as defined in Section 6.8.2.3 Message Control for MSI-X in the PCI Local Bus Specification, Rev. 3.0. The following fields are defined:

  • MsixIntfc_o[15]: Enable
  • MsixIntfc_o[14]: Mask
  • MsixIntfc_o[13:11]: Reserved
  • MsixIntfc_o[10:0]: Table size
IntxReq_i

Input

When asserted, the Endpoint is requesting attention from the interrupt service routine unless MSI or MSI-X interrupts are enabled. Remains asserted until the device driver clears the pending request.
IntxAck_o

Output

This signal is the acknowledge for IntxReq_i. It is asserted for at least one cycle either when either of the following events occur:

  • The Assert_INTA message TLP has been transmitted in response to the assertion of the IntxReq_i.
  • The Deassert_INTA message TLP has been transmitted in response to the deassertion of the IntxReq_i signal.

Refer to the timing diagrams below.

The following figure illustrates interrupt timing for the legacy interface. In this figure the assertion of IntxReq_i instructs the Hard IP for PCI Express to send an Assert_INTA message TLP.

Figure 11. Legacy Interrupt Assertion

The following figure illustrates the timing for deassertion of legacy interrupts. The assertion of IntxReq_i instructs the Hard IP for PCI Express to send a Deassert_INTA message.

Figure 12. Legacy Interrupt Deassertion

The following figure illustrates the timing for deassertion of legacy interrupts. The assertion of IntxReq_i instructs the Hard IP for PCI Express to send a Deassert_INTA message.

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