Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support

If you select Enable multiple MSI/MSI X support under the Avalon-MM System Settings banner in the parameter editor, the Hard IP for PCI Express exports the MSI, MSI‑X, and INTx interfaces to the Application Layer. The Application Layer must include a Custom Interrupt Handler to send interrupts to the Root Port. You must design this Custom Interrupt Handler. The following figure provides an overview of the logic for the Custom Interrupt Handler. The Custom Interrupt Handler should include hardware to perform the following tasks:

  • An MSI/MXI-X IRQ Avalon‑MM Master port to drive MSI or MSI-X interrupts as memory writes to the PCIe Avalon‑MM bridge.
  • A legacy interrupt signal, IntxReq_i, to drive legacy interrupts from the MSI/MSI‑X IRQ module to the Hard IP for PCI Express.
  • An MSI/MSI‑X Avalon‑MM Slave port to receive interrupt control and status from the PCIe Root Port.
  • An MSI-X table to store the MSI-X table entries. The PCIe Root Port sets up this table.
Figure 29. Block Diagram for Custom Interrupt Handler

Refer to Interrupts for Endpoints for the definitions of MSI, MSI‑X, and INTx buses.

For more information about implementing MSI or MSI‑X interrupts, refer to the PCI Local Bus Specification, Revision 2.3, MSI-X ECN.

For more information about implementing interrupts, including an MSI design example, refer to Handling PCIe Interrupts on the Intel® FPGA wiki.

Did you find the information on this page useful?

Characters remaining:

Feedback Message