Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

2.7. Compiling the Design in the Quartus® Prime Software

To compile the Qsys design example in the Quartus® Prime software, you must create a Quartus® Prime project and add your Qsys files to that project.

Complete the following steps to create your Quartus® Prime project:

  1. Click the New Project Wizard icon.
  2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you previously turned it off)
  3. On the Directory, Name, Top-Level Entity page, enter the following information:
    1. The working directory shown is correct. You do not have to change it.
    2. For the project name, browse to the synthesis directory that includes your Qsys project, <working_dir>/ep_g1x4/synthesis. Select your variant name, ep_g1x4.v. Then, click Open.
    3. If the top‑level design entity and Qsys system names are identical, the Quartus® Prime software treats the Qsys system as the top‑level design entity.
  4. Click Next to display the Add Files page.
  5. Complete the following steps to add the Quartus® Prime IP File (.qip)to the project:
    1. Click the browse button. The Select File dialog box appears.
    2. In the Files of type list, select IP Variation Files (*.qip).
    3. Browse to the <working_dir>/ep_g1x4/synthesis directory.
    4. Click ep_g1x4.qip and then click Open.
    5. On the Add Files page, click Add, then click OK.
  6. Click Next to display the Device page.
  7. On the Family & Device Settings page, choose the following target device family and options:
    1. In the Family list, select Cyclone V (E/GX/GT/SX/SE/ST)
    2. In the Devices list, select Cyclone V GX Extended Features..
    3. In the Available Devices list, select 5CGXFC7D6F31C7.
  8. Click Next to close this page and display the EDA Tool Settings page.
  9. From the Simulation list, select ModelSim ®. From the Format list, select the HDL language you intend to use for simulation.
  10. Click Next to display the Summary page.
  11. Check the Summary page to ensure that you have entered all the information correctly.
  12. Click Finish to create the Quartus® Prime project.
  13. Add the Synopsys Design Constraint (SDC) commands shown in the following example to the top‑level design file for your Quartus® Prime project.
  14. To compile your design using the Quartus® Prime software, on the Processing menu, click Start Compilation. The Quartus® Prime software then performs all the steps necessary to compile your design.

  15. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note whether the timing constraints are achieved in the Compilation Report.
  16. If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design Space Explorer on the tools menu.

Synopsys Design Constraints


create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*}
derive_pll_clocks
derive_clock_uncertainty

# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# Modify to match the actual clock pin name
# used for this clock, and also changed to have the correct period set
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}

Files Generated for Altera IP Cores

Figure 6. IP Core Generated FilesThe Quartus® Prime software generates the following output for your IP core.
Note: By following these instructions you create all the files for simulation and synthesis. However, this design example does not generate all the files necessary to download the design example to hardware. Refer to AN 456 PCI Express High Performance Reference Design for a design that includes all files necessary to download your design to an Cyclone V FPGA Development Kit.

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