Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Document Table of Contents

4.3. Reset Signals

Refer to Reset and Clocks for more information about the reset sequence and a block diagram of the reset logic.

Table 22.  Reset Signals






Active low reset signal. In the Altera hardware example designs, npor is the OR of pin_perst and local_rstn coming from the software Application Layer. If you do not drive a soft reset signal from the Application Layer, this signal must be derived from pin_perst. You cannot disable this signal. Resets the entire IP Core and transceiver. Asynchronous.

In systems that use the hard reset controller, this signal is edge, not level sensitive; consequently, you cannot use a low value on this signal to hold custom logic in reset. For more information about the hard and soft reset controllers, refer to the Reset and Clocks chapter.



Active low reset signal. It is derived from npor or pin_perstn. When asserted, this signal indicates that the Hard IP is in reset. The nreset_status signal is synchronous to the pld_clk clock and is deasserted only when npor is deasserted and the Hard IP for PCI Express is not in reset. Use nreset_status to drive the reset of your application.


Active low reset from the PCIe reset pin of the device. pin_perst resets the datapath and control registers. This signal is required for Configuration via Protocol (CvP). For more information about CvP refer to Configuration via Protocol (CvP).

Cyclone V have 1 or 2 instances of the Hard IP for PCI Express. Each instance has its own pin_perst signal. You must connect the pin_perst of each Hard IP instance to the corresponding nPERST pin of the device. These pins have the following locations:

  • nPERSTL0: top left Hard IP
  • nPERSTL1: bottom left Hard IP and CvP blocks

For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to nPERSL1.

For maximum use of the Cyclone® V device, Altera recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link.

Refer to the appropriate device pinout for correct pin assignment for more detailed information about these pins. The PCI Express Card Electromechanical Specification 2.0 specifies this pin requires 3.3 V. You can drive this 3.3V signal to the nPERST* even if the VVCCPGM of the bank is not 3.3V if the following 2 conditions are met:

  • The input signal meets the VIH and VIL specification for LVTTL.

    The input signal meets the overshoot specification for 100°C operation as specified by the “Maximum Allowed Overshoot and Undershoot Voltage” in the Device Datasheet for Cyclone V Devices.

Figure 10. Reset and Link Training Timing Relationships

The following figure illustrates the timing relationship between npor and the LTSSM L0 state.

Note: To meet the 100 ms system configuration time, you must use the fast passive parallel configuration scheme with and a 32-bit data width (FPP x32).

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