Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

4.6.2.1. Configuration Space Register Access

The tl_cfg_ctl signal is a multiplexed bus that contains the contents of Configuration Space registers as shown in the figure below. Information stored in the Configuration Space is accessed in round robin order where tl_cfg_add indicates which register is being accessed. The following table shows the layout of configuration information that is multiplexed on tl_cfg_ctl.

Figure 13. Multiplexed Configuration Register Information Available on tl_cfg_ctl Fields in blue are available only for Root Ports.
Table 29.  Configuration Space Register Descriptions

Register

Width

Direction

Description

cfg_dev_ctrl_func<n>

16

Output

cfg_dev_ctrl_func<n>[15:0] is Device Control register for the PCI Express capability structure.
cfg_dev_ctrl2

16

Output

cfg_dev2ctrl[15:0] is Device Control 2 for the PCI Express capability structure.

cfg_slot_ctrl

16

Output

cfg_slot_ctrl[15:0] is the Slot Status of the PCI Express capability structure. This register is only available in Root Port mode.

cfg_link_ctrl

16

Output

cfg_link_ctrl[15:0]is the primary Link Control of the PCI Express capability structure.

For Gen2 operation, you must write a 1’b1 to the Retrain Link bit (Bit[5] of the cfg_link_ctrl) of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 L0 state. Retraining directs the LTSSM to the Recovery state. Retraining to a higher data rate is not automatic for the Cyclone V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.

cfg_link_ctrl2

16

Output

cfg_link_ctrl2[31:16] is the secondary Link Control register of the PCI Express capability structure for Gen2 operation.

When tl_cfg_addr=4'b0010, tl_cfg_ctl returns the primary and secondary Link Control registers, { {cfg_link_ctrl[15:0], cfg_link_ctrl2[15:0]}. The primary Link Status register contents are available on tl_cfg_sts[46:31].

For Gen1 variants, the link bandwidth notification bit is always set to 0. For Gen2 variants, this bit is set to 1.

cfg_prm_cmd_func<n>

16

Output

Base/Primary Command register for the PCI Configuration Space.

cfg_root_ctrl

8

Output

Root control and status register of the PCI Express capability. This register is only available in Root Port mode.

cfg_sec_ctrl

16

Output

Secondary bus Control and Status register of the PCI Express capability. This register is available only in Root Port mode.

cfg_secbus

8

Output

Secondary bus number. This register is available only in Root Port mode.

cfg_subbus

8

Output

Subordinate bus number. This register is available only in Root Port mode.

cfg_msi_addr

64

Output

cfg_msi_add[63:32] is the message signaled interrupt (MSI) upper message address. cfg_msi_add[31:0] is the MSI message address.

cfg_io_bas

20

Output

The upper 20 bits of the I/O limit registers of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_io_lim

20

Output

The upper 20 bits of the IO limit registers of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_np_bas

12

Output

The upper 12 bits of the memory base register of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_np_lim

12

Output

The upper 12 bits of the memory limit register of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_pr_bas

44

Output

The upper 44 bits of the prefetchable base registers of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_pr_lim

44

Output

The upper 44 bits of the prefetchable limit registers of the Type1 Configuration Space. Available in Root Port mode.

cfg_pmcsr

32

Output

cfg_pmcsr[31:16] is Power Management Control and cfg_pmcsr[15:0]is the Power Management Status register.

cfg_msixcsr

16

Output

MSI-X message control.

cfg_msicsr

16

Output

MSI message control. Refer to the following table for the fields of this register.

cfg_tcvcmap

24

Output

Configuration traffic class (TC)/virtual channel (VC) mapping. The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet.

  • cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
  • cfg_tcvcmap[5:3]: Mapping for TC1.
  • cfg_tcvcmap[8:6]: Mapping for TC2.
  • cfg_tcvcmap[11:9]: Mapping for TC3.
  • cfg_tcvcmap[14:12]: Mapping for TC4.
  • cfg_tcvcmap[17:15]: Mapping for TC5.
  • cfg_tcvcmap[20:18]: Mapping for TC6.
  • cfg_tcvcmap[23:21]: Mapping for TC7.
cfg_msi_data

16

Output

cfg_msi_data[15:0] is message data for MSI.

cfg_busdev

13

Output

Bus/Device Number captured by or programmed in the Hard IP.

Figure 14. Configuration MSI Control Status Register
Table 30.   Configuration MSI Control Status Register Field Descriptions

Bit(s)

Field

Description

[15:9]

Reserved

N/A

[8]

mask capability

Per-vector masking capable. This bit is hardwired to 0 because the function does not support the optional MSI per-vector masking using the Mask_Bits and Pending_Bits registers defined in the PCI Local Bus Specification. Per-vector masking can be implemented using Application Layer registers.

[7]

64-bit address capability

64-bit address capable.

  • 1: function capable of sending a 64-bit message address
  • 0: function not capable of sending a 64-bit message address

[6:4]

multiple message enable

This field indicates permitted values for MSI signals. For example, if “100” is written to this field 16 MSI signals are allocated.

  • 3’b000: 1 MSI allocated
  • 3’b001: 2 MSI allocated
  • 3’b010: 4 MSI allocated
  • 3’b011: 8 MSI allocated
  • 3’b100: 16 MSI allocated
  • 3’b101: 32 MSI allocated
  • 3’b110: Reserved
  • 3’b111: Reserved

[3:1]

multiple message capable

This field is read by system software to determine the number of requested MSI messages.

  • 3’b000: 1 MSI requested
  • 3’b001: 2 MSI requested
  • 3’b010: 4 MSI requested
  • 3’b011: 8 MSI requested
  • 3’b100: 16 MSI requested
  • 3’b101: 32 MSI requested
  • 3’b110: Reserved

[0]

MSI Enable

If set to 0, this component is not permitted to use MSI.

In designs that support multiple functions, host software should not use the MSI Enable bit to mask a function’s MSI’s. Doing so, may leave an MSI request from one function in the pending state, blocking the MSI requests of other functions.

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