Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide

ID 683494
Date 3/19/2020
Public
Document Table of Contents

4.6.2. Hard IP Status Extension

Table 27.  Hard IP Status Extension SignalsThis optional bus adds signals that are useful for debugging to the top-level variant, including:
  • The most important native Avalon-ST RX signals
  • The Configuration Space signals
  • The BAR
  • The ECC error
  • The signal indicating that the pld_clk is in use

Signal

Direction

Description

pld_clk_inuse

Output

When asserted, indicates that the Hard IP Transaction Layer is using the pld_clk as its clock and is ready for operation with the Application Layer. For reliable operation, hold the Application Layer in reset until pld_clk_inuse is asserted.

pme_to_sr

Output

Power management turn off status register.

Root Port—This signal is asserted for 1 clock cycle when the Root Port receives the pme_turn_off acknowledge message.

Endpoint—This signal is asserted for 1 cycle when the Endpoint receives the PME_turn_off message from the Root Port.

rx_st_bar[7:0]

Output

The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, and IORD TLPs. Ignored for the completion or message TLPs. Valid during the cycle in which rx_st_sop is asserted.

The following encodings are defined for Endpoints:

  • Bit 0: BAR 0
  • Bit 1: BAR 1
  • Bit 2: Bar 2
  • Bit 3: Bar 3
  • Bit 4: Bar 4
  • Bit 5: Bar 5
  • Bit 6: Reserved
  • Bit 7: Reserved

The following encodings are defined for Root Ports:

  • Bit 0: BAR 0
  • Bit 1: BAR 1
  • Bit 2: Primary Bus number
  • Bit 3: Secondary Bus number
  • Bit 4: Secondary Bus number to Subordinate Bus number window
  • Bit 5: I/O window
  • Bit 6: Non-Prefetchable window
  • Bit 7: Prefetchable window
rx_st_data[<n>-1:0]

Output

Receive data bus. Note that the position of the first payload DWORD depends on whether the TLP address is qword aligned. The mapping of message TLPs is the same as the mapping of TLPs with 4‑DWORD headers.

rx_st_eop

Output

Indicates that this is the last cycle of the TLP when rx_st_valid is asserted.

rx_st_err

Output

Indicates that there is an ECC error in the internal RX buffer. Active when ECC is enabled. ECC is automatically enabled by the Quartus® Prime assembler. ECC corrects single‑bit errors and detects double‑bit errors on a per byte basis.

When an uncorrectable ECC error is detected, rx_st_err is asserted for at least 1 cycle while rx_st_valid is asserted.

Intel recommends resetting the Cyclone V Hard IP for PCI Express when an uncorrectable double‑bit ECC error is detected.

rx_st_sop

Output

Indicates that this is the first cycle of the TLP when rx_st_valid is asserted.

rx_st_valid

Output

Clocks rx_st_data into the Application Layer. Deasserts within 2 clocks of rx_st_ready deassertion and reasserts within 2 clocks of rx_st_ready assertion if more data is available to send.

serr_out

Output

System Error: This signal only applies to Root Port designs that report each system error detected, assuming the proper enabling bits are asserted in the Root Control and Device Control registers. If enabled, serr_out is asserted for a single clock cycle when a system error occurs. System errors are described in the PCI Express Base Specification 2.1 or 3.0 in the Root Control register.

tl_cfg_add[3:0]

Output

Address of the register that has been updated. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl.

tl_cfg_ctl[31:0]

Output

The tl_cfg_ctl signal is multiplexed and contains the contents of the Configuration Space registers. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl.
tl_cfg_sts[52:0]

Output

Configuration status bits. This information updates every pld_clk cycle. The following table provides detailed descriptions of the status bits.

tx_st_ready

Output

Indicates that the Transaction Layer is ready to accept data for transmission. The core deasserts this signal to throttle the data stream. tx_st_ready may be asserted during reset. The Application Layer should wait at least 2 clock cycles after the reset is released before issuing packets on the Avalon‑ST TX interface. The reset_status signal can also be used to monitor when the IP core has come out of reset.

If asserted by the Transaction Layer on cycle <n>tx_st_ready , then <n + readyLatency> is a ready cycle, during which the Application Layer may assert tx_st_valid and transfer data.

When tx_st_ready, tx_st_valid and tx_st_data are registered (the typical case), Intel recommends a readyLatency of 2 cycles to facilitate timing closure; however, a readyLatency of 1 cycle is possible. If no other delays are added to the read‑valid latency, the resulting delay corresponds to a readyLatency of 2.

Table 28.  Mapping Between tl_cfg_sts and Configuration Space Registers

tl_cfg_sts

Configuration Space Register

Description

[52:49]

Device Status Register[3:0]

Records the following errors:

  • Bit 3: unsupported request detected
  • Bit 2: fatal error detected
  • Bit 1: non‑fatal error detected
  • Bit 0: correctable error detected

[48]

Slot Status Register[8]

Data Link Layer state changed

[47]

Slot Status Register[4]

Command completed. (The hot plug controller completed a command.)

Note: For Root Ports, you enable the Slot register by turning on Use Slot Power Register in the parameter editor. When enabled, access to Command Completed Interrupt Enable bit of the Slot Control register remains Read/Write. This bit should be hardwired to 1b'0. You should not write this bit.

[46:31]

Link Status Register[15:0]

Records the following link status information:

  • Bit 15: link autonomous bandwidth status
  • Bit 14: link bandwidth management status
  • Bit 13: Data Link Layer link active
  • Bit 12: Slot clock configuration
  • Bit 11: Link Training
  • Bit 10: Undefined
  • Bits[9:4]: Negotiated Link Width
  • Bits[3:0] Link Speed

[30]

Link Status 2 Register[0]

Current de-emphasis level.

[29:25]

Status Register[15:11]

Records the following 5 primary command status errors:

  • Bit 15: detected parity error
  • Bit 14: signaled system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signaled target abort

[24]

Secondary Status Register[8]

Master data parity error

[23:6]

Root Status Register[17:0]

Records the following PME status information:

  • Bit 17: PME pending
  • Bit 16: PME status
  • Bits[15:0]: PME request ID[15:0]

[5:1]

Secondary Status Register[15:11]

Records the following 5 secondary command status errors:

  • Bit 15: detected parity error
  • Bit 14: received system error
  • Bit 13: received master abort
  • Bit 12: received target abort
  • Bit 11: signaled target abort

[0]

Secondary Status Register[8]

Master Data Parity Error

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