AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

Functional Description for the Drive-On-Chip Reference Design

Figure 6. Block Diagram for MAX 10 FPGA Development Boards
Note: Only the multiaxis power board can drive four motors.
Figure 7. Block Diagram for Cyclone V SoC Development Board and SoCKit

The Qsys system consists of:

  • DC link monitor
  • FOC subsystem
  • FFTs (SoC only)
  • Processor subsystem
  • Four drive channels comprising the following motor control peripheral components:
    • 6-channel PWM
    • ADC interface
    • Drive system monitor
    • Encoder interface (BiSS or EnDat)

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