AN 669: Drive-On-Chip Design Example for Cyclone V Devices

ID 683466
Date 5/15/2022
Public
Document Table of Contents

Nios II Subsystem for MAX 10 FPGA Development Kits

The Drive-On-Chip reference design Nios II subsystem comprises the following Qsys components for a fully functional processor system with debugging capabilities:
  • Nios II fast processor
  • Floating-point hardware custom instructions 2 (optional)
  • Tightly coupled instruction and data memory
  • JTAG master
  • Performance counters
  • Clocking and bridge
  • SDRAM controller
  • JTAG UART
  • System console debugging RAM
  • Debugging dump memory

The ISR uses the tightly coupled memory blocks for code and data to ensure fast predictable execution time for the motor control algorithm.

The Nios II subsystem uses the JTAG master and debug memories to allow real-time interactions between System Console and the processor. The reference design uses the System Console debugging RAM to send commands and receive status information. The debugging dump memory stores trace data that you can display as time graphs in System Console.

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