DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.13.20. Reinterpret Cast for Bit Packing and Unpacking

This design example demonstrates the ReinterpretCast block, which packs signals into a long word and extracts multiple signals from a long word.

The first datapath reinterprets a single precision complex signal into raw 32-bit components that separate into real and imaginary parts. A BitCombine block then merges it into a 64-bit signal. The second datapath uses the BitExtract block to split a 64-bit wide signal into a two component vectors of 32-bit signals. The ReinterpretCast block then converts the raw bit pattern into single-precision IEEE format. The HDL that the design synthesizes is simple wire connections, which performs no computation.

The model file is demo_reinterpret_cast.mdl.