DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
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Document Table of Contents
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8.6. How to Manage Latency

The Primitive library blocks are untimed circuits, so they are not cycle accurate. A one-to-one mapping does not exist between the blocks in the Simulink model and the blocks you implement in your design in RTL. This decoupling of design intent from design implementation gives productivity benefits. The ChannelOut block is the boundary between the untimed section and the cycle accurate section. This block creates the additional delay that the RTL introduces, so that data going in to the ChannelOut block delays internally, before DSP Builder presents it externally. The latency of the block shows on the ChannelOut mask. You may want to fix or constrain the latency after you complete part of a DSP Builder design, for example on an IP library block or for a Primitive subsystem. In other cases, you may want to limit the latency in advance, which allows future changes to other subsystems without causing undesirable effects upon the overall design.

To accommodate extra latency, insert registers. This feature applies only to Primitive subsystems. To access, use the Synthesis Info block.

Latency is the number of delays in the valid signal across the subsystem. The DSP Builder advanced blockset balances delays in the valid and channel path with delays that DSP Builder inserts for autopipelining in the datapath.

Note: User-inserted sample delays in the datapath are part of the algorithm, rather than pipelining, and are not balanced. However, any uniform delays that you insert across the entire datapath optimize out. If you want to constrain the latency across the entire datapath, you can specify this latency constraint in the SynthesisInfo block.