DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
Public

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6.15.3. Four Channel, Four Banks NCO

This design example implements a NCO with four channels and four banks.

This design example is similar to the Four Channel, Two Banks NCO design, but it has four banks of frequencies defined for the phase increment values. Each spectrum plot has five peaks: the fifth peak shows the changes the design example writes through the memory interface.

The design example uses a 32-bit memory interface with a 24-bit accumulator. Hence, the design example requires only one phase increment memory register for each phase increment value—refer to the address and data setup on the BusStimulus block inside this design example.

This design example has four banks of frequencies with each bank processed for 2,000 steps before switching to the other. You should write a new value into the phase increment memory register for each bank to change the NCO output frequencies after 16,000 steps during simulation. To avoid writing new values to the active bank, the design example configures the write enable signals in the following way:

[zeros(1,15000) 1 zeros(1,2000) 1 zeros(1,2000) 1 zeros(1,2000) 1 zeros(1,8000)]

This configuration ensures that a new phase increment value for bank 0 is written at 15000 steps when the NCO is processing bank 3; a new phase increment value for bank 1 is written at 17000 steps when the NCO is processing bank 0; a new phase increment value for bank 2 is written at 19000 steps when the NCO is processing bank 1; and a new phase increment value for bank 3 is written at 21000 steps when the NCO is processing bank 2.

There is one write for each bank to write a new value for channel 1 into bank 0; a new value for channel 2 into bank 1; a new value for channel 3 into bank 2; and a new value for channel 4 into bank 3. Each new phase value needs only one register due to the size of the memory interface.

The top-level testbench includes Control, Signals, BusStimulus, Run ModelSim, and Run Quartus Prime blocks, plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_4banks_mem_interface.m script.

The NCOSubSystem subsystem includes the Device and NCO blocks.

The model file is demo_mc_nco_4banks_mem_interface.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.