DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

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Document Table of Contents

10.6.1. Creating a Sine Wave Generator in DSP Builder


  1. In Simulink, click DSP Builder > New Model wizard and create a floating-point primitive (simple) model.
  2. Create a primitive subsystem with the following components:
    • ChannelIn and ChannelOut
    • SynthesisInfo (configure to Scheduled)
    • Counter with a large period (e.g. 32,768) and incrementing in steps of 1
    • Convert block (set the mask parameter Output data type mode to single)
    • Mult block
    • Trig block (configure the Mask parameter function to sin(x))
  3. Connect the blocks.
  4. Simulate the design.
  5. Connect the single-precision input of the subsystem to a Simulink built-in source. For example, repeating sequence stair.
  6. Set the repeating sequence stair block parameter Output Data Type to single. Hence, both inputs to the Mult block are single. This data type propagates through to the Trig block
  7. Simulate this design with hardware generation turned on. DSP Builder generates HDL files for a single-precision IEEE multiply, a single-precision sine function, and a fixed-to-float conversion component.
  8. Click DSP Builder > Resource Usage > Resource Usage Report and record the DSP and LUT usage for the design.
  9. To change the floating-point precision of the synthesized design, insert a Convert block on the floating-point input wire.
  10. Parameterize the Convert block:
    1. Set Output data type mode to Variable precision floating point.
    2. In the Floating Point Precision drop-down menu select float26_m17.
  11. Apply the same parameters to the Convert block in the primitive subsystem.
  12. To connect the floating-point output port of the subsystem to a scope, or some other built-in Simulink sink block:
    1. Insert a Convert block on the floating-point output wire.
    2. Set the Output data type mode to double.
      Note: If you do not connect a Convert block, you cannot simulate your design. Simulink scopes do not recognize the DSP Builder custom floating-point type.
  13. Simulate the design to generate HDL for the reduced precision multiplier, sine function, and fixed-to-float convert.
  14. Re-examine the resource usage report. The DSP and LUT utilization is significantly lower than for the single-precision design.