DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.6.11. Set-Priority Latch (SRlatch)

DSP Builder offers two single-cycle latency latch subsystems for common operations for the valid signal, latching with set and reset. The SRlatch block gives priority to the reset input signal. The SRlatch_PS block gives priority to the set input signal. In both blocks if set and reset inputs are both zero the current output state is maintained.
Table 280.  Truth Table for SRlatch
S R q
0 0 q
1 0 1
0 1 0
1 1 1