14.6.7. Nested Loops (NestedLoop1, NestedLoop2, NestedLoop3)

DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

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Date 12/04/2023

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14.6.7. Nested Loops (NestedLoop1, NestedLoop2, NestedLoop3)

The DSP Builder NestedLoop1, NestedLoop2, and NestedLoop3 blocks maintain a set of counters that implement the equivalent of a nested for loop in software. They provide more flexibility than the Loop block and greater readability and lower latency than ForLoop blocks.

DSP Builder implements the NestedLoop blocks as masked subsystems and use existing DSP Builder Primitive library blocks. They do not have fixed implementations. DSP Builder generates a new implementation at runtime whenever you change any of the loop specifications.

For each loop in a NestedLoop block, you can specify start, increment, and end expressions. Each of these expressions may have one of the following three forms:

A constant expression that evaluates (in the MATLAB base environment) to an integer. For example, if the MATLAB variable N has the value 256, (log2(N)+1) is a legal expression (and evaluates to 9).
An instance of the loop variable controlling an enclosing loop. For example, you can use "i" (the outer loop variable) as the start expression of the "j" or "k" loops.
A port name, optionally accompanied by a width specification in angle brackets. For example "p" or "q<4>". If no width is specified, it defaults to 8. This option generates a new input port (with the user-defined name and width) on the NestedLoop block.

For a NestedLoop2 block, with user-supplied start, increment, and end expressions of S1, I1 and E1 (for the outer loop) and S2, I2 and E2 (for the inner loop), the equivalent C++ code is:

	int i = S1;
	do {
		int j = S2;
		do {
			j += I2;
		} while (j != E2);
		i += I1;
	} while (i != E1);

Each NestedLoop block has two fixed input ports (go and en) and a variable number of additional user-defined input ports. DSP Builder regards each user-defined port as a signed input.

Each block also has two fixed output ports (qv and ql) and one (NestedLoop1), two (NestedLoop2) or three (NestedLoop3) output ports for the counter values.

When the input en signal is low (inactive), the output qv (valid) signal is also set low. The state of the NestedLoop block does not change, even if it receives a go signal.

Normal operation occurs when the en signal is high. The NestedLoop block can be in the waiting or counting state.

The NestedLoop block resets into the waiting state and remains there until it receives a go signal. While in the waiting state, the qv signal is low and the value of the other outputs are undefined.

When the block receives a go signal, the NestedLoop block transitions into the counting state. The counters start running and the qv ouput signal is set high. When all the counters eventually reach their final values, the ql (last cycle) output becomes high. On the following cycle, the NestedLoop block returns to the waiting state until it receives another go signal.

If the block receives a go signal while the NestedLoop block is already in the counting state, it remains in the counting state but all its counters are reset to their start values.

Observe the following points:

All counters in the NestedLoop block are signed. To effectively use unsigned counters, zero-extend any unsigned inputs (and correspondingly increase their width specifications) by one bit.
The end test is an equality test. Each loop continues until the current value of the counter is equal to the end value. However, if the loop counter overflows, the subsequent behavior of the NestedLoop block is undefined.
The end values are inclusive. So setting the start value to 0, the increment to 1 and the end value to 10 actually produces 11 iterations of the loop.
The previous two factors means that every loop iterates at least once. NestedLoop blocks (unlike ForLoop blocks) do not support empty loops.

When you use user-defined ports to supply loop control values, the values on these ports must be held constant while the NestedLoop block is in its counting state. Otherwise the block produces undefined behavior.

Table 278. NestedLoop Block Port interface
Signal	Direction	Type	Description	Vector Data Support	Complex Data Support
`go`	Input	Boolean	Go.	No	No
`en`	Input	Boolean	Enable.	No	No
`?`	Input	Signed integer	Loop control values.	No	No
`qv`	Output	Boolean	Valid.	No	No
`ql`	Output	Boolean	Last iteration flag.	No	No
`i`	Output	Signed integer	Outer loop count.	No	No
`j`	Output	Signed integer	Middle loop count. (`NestedLoop2` only).	No	No
`k`	Output	Signed integer	Inner loop count (`NestedLoop3` only).	No	No

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DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

14.6.7. Nested Loops (NestedLoop1, NestedLoop2, NestedLoop3)