DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
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3.7.4. DSP Builder Designs in Platform Designer

DSP Builder generates hardware Tcl (_hw.tcl) files describing the generated IP. You can use the hardware Tcl file to integrate the DSP Builder design with other components to build a larger system in Platform Designer.

A DSP Builder design may have the following Platform Designer interfaces:

  • Avalon memory-mapped. An Avalon memory-mapped interface is generated if your design has any blocks from the Memory-Mapped Library or some IP such as the FIR filter.
  • Avalon streaming. Avalon streaming interfaces are generated if your design has any Avalon Streaming blocks from the Streaming Library.
  • AXI4 streaming. AXI4 streaming interfaces are generated if your design has any AXI4 streaming blocks from the Streaming Library.
  • Conduit. One or more conduit interfaces are generated for all other device level