DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

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14.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X)

The FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X blocks implement fully-parallel FFTs (or iFFTs) for 2, 4, 8, 16, 32, and 64 points respectively.

Unlike the corresponding P blocks (FFT2P, FFT4P, etc), they implement both FFTs and iFFTs and offer flexible ordering of the input and output wires.

Each block can also be internally parallelized to process several FFTs at once. For example, if there are 16 wires, each FFT8P block can calculate two 8-point FFTs (by specifying the number of spatial bits to be 4). With 32 wires, the same block can calculate four 8-point FFTs (by specifying the number of spatial bits to be 5).

Not all parameters are available with all blocks.

Table 121.  Parameters for the FFT2X Blocks
Parameter Description
iFFT true to implement an IFFT, otherwise false.
Number of spatial bits M for 2M wires.
Bit-reversed input true if you expect bit-reversed input, otherwise false.
Bit-reversed output true if you want bit-reversed output, otherwise false.
Twiddle/pruning specification(  
Use faithful rounding true if the block uses faithful (rather than correct) rounding for floating-point operations. Fixed-point FFTs ignore this parameter.
Table 122.  Port Interface for the FFT2X Blocks
Signal Direction Type Description
v Input Boolean. Valid input signal.
d Input Any complex. Complex data input signal.
qv Output Boolean. Valid output signal.
q Output Determined by pruning specification. Complex data output signal.