DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
Public

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8.4.3. Example DSP Builder Custom Scripts

You can write scripts that directly change parameters (such as the hardware destination directory) on the Control and Signals blocks.

For example, in a script that passes the design name (without .mdl extension) as model you can use:

%% Load the model
load_system(model);
%% Get the Signals block
signals = find_system(model, 'type', 'block', 'MaskType', 'DSP Builder Advanced Blockset Signals Block');
if (isempty(signals)) 
   error('The design must contain a Signals Block. ');
end;
%% Get the Controls block
control = find_system(model, 'type', 'block', 'MaskType', 'DSP Builder Advanced Blockset Control Block');
if (isempty(control)) 
   error('The design must contain a Control Block. ');
end;%% 
Example: set the RTL destination directory
dest_dir = ['../rtl' num2str(freq)];
dspba.SetRTLDestDir(model, rtlDir);

Similarly you can get and set other parameters. For example, on the Signals block you can set the target clock frequency:

fmax_freq = 300.0; dspba.set_param(signals{1},'freq', fmax_freq);

You can also change the following threshold values that are parameters on the Control block:

  • distRamThresholdBits
  • hardMultiplierThresholdLuts
  • mlabThresholdBits
  • ramThresholdBits

You can loop over changing these values, change the destination directory, run the Quartus Prime software each time, and perform design space exploration. For example:

%% Run a simulation; which also does the RTL generation.
t = sim(model);
%% Then run the Quartus Prime compilation flow.
[success, details] = run_hw_compilation(<model>, './')%% 
where details is a struct containing resource and timing information 
   details.Logic, 
   details.Comb_Aluts, 
   details.Mem_Aluts, 
   details.Regs, 
   details.ALM, 
   details.DSP_18bit, 
   details.Mem_Bits, 
   details.M9K, 
   details.M144K, 
   details.IO, 
   details.FMax, 
   details.Slack, 
   details.Required, 
   details.FMax_unres, 
   details.timingpath, 
   details.dir, 
   details.command, 
   details.pwd
such that >> disp(details) gives output something like: 
   Logic: 4915 
   Comb_Aluts: 3213 
   Mem_Aluts: 377 
   Regs: 4725 
   ALM: 2952 
   DSP_18bit: 68 
   Mem_Bits: 719278 
   M9K: 97 
   M144K: 0 IO: 116 
   FMax: 220.1700 
   Slack: 0.4581 
   Required: 200 
   FMax_unres: 220.1700 
   timingpath: [1x4146 char] 
   dir: '../quartus_demo_ifft_4096_for_SPR_FFT_4K_n_2' 
   command: [1x266 char] 
   pwd: 'D:\test\script'
Note: The Timing Report is in the timingpath variable, which you can display by disp(details.timingpath). Unused resources may appear as -1, rather than 0.

You must previously execute load_system before commands such as find_system and run_hw_compilation work.

A useful set of commands to generate RTL, compile in the Quartus Prime software and return the details is:

load_system(<model>);
sim(<model>);
[success, details] = run_hw_compilation(<model>, './')