DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

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Document Table of Contents Real-Time Hardware Verification Design Example

You can verify your DSP Builder design in hardware by sampling real-time data with the demo_sil_nco design example. This design uses a MATLAB GUI to control and capture real-time data from an NCO running at full clock rate in an FPGA.

The GUI is a MATLAB app, and uses the DSP Builder System Console API to set the desired frequency and capture sample data in a loop. The design:

  1. Triggers capture
  2. Polls data ready register
  3. Reads captured data
  4. Uses MATLAB to calculate and plot an FFT
Figure 37. NCO
Figure 38. Capture buffers with control registers
Figure 39. Address and capture logic
Figure 40. Platform Designer system
Figure 41. System Console in MATLAB App to Implement GUI