DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
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Document Table of Contents
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6.10.1. Memory-Mapped Registers

This design example is an extreme example of using the processor registers to implement a simple calculator. Registers and shared memories write arguments and read results.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks.

This design also includes BusStimulus and BusStimulusFileReader blocks.

The RegChip subsystem includes RegField, RegBit, RegOut, SharedMem, Const, Add, Sub, Mult, Convert, Select, BitExtract, Shift, and SynthesisInfo blocks.

The model file is demo_regs.mdl.