DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
Public
Document Table of Contents

6.13.22. Square Root Using CORDIC

This design example demonstrates the CORDIC block. It configures the CORDIC block for uint(32) input and uint(16) output. The example is partially parallelized (four stages).

The design example allows you to generate a valid signal. The design example only generates output and can only accept input every N cycles, where N depends on the number of stages, the data output format, and the target fMAX. The valid signal goes high when the output is ready. You can use this output signal to trigger the next input, for example, a FIFO buffer read for bursty data.

The model file is demo_cordic_sqrt.mdl.