DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

6.4.2. Decimating CIC Filter

This design example implements a decimating CIC filter.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks, plus ChanView block that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_dcic.m script.

The CICSystem subsystem includes the Device and DecimatingCIC blocks.

The model file is demo_dcic.mdl.

Note: This design example uses the Simulink Signal Processing Blockset.