DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

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Document Table of Contents Batch Hardware Verification Design Example

You can verify your design in hardware by exercising the unit under test with batches of data that create input and output buffers.

Each test:

  1. Generates test data in MATLAB
  2. Uses System Console API to write test data to input buffer and trigger test
  3. Uses System Console API to read result from output buffer
  4. Uses MATLAB to compare result to a golden reference

DSP Builder design example for off chip source and sink buffers.

Figure 32. Top-Level SystemShows source and sink buffers and DUT.
Figure 33. Source Buffer AddressGen block triggers reads from SharedMem to drive DUT input. RegField initiates execution of the AddressGen block from host.
Figure 34. Sink Buffer
Figure 35.  Platform Designer System master_0 is the instance of JTAG debug master. syscon_api_sil_ex_0 is the instance of the top-level DSP Builder system, which contains test buffers.
Figure 36. MATLAB API