DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.3.15. Multiwire Transpose (MultiwireTranspose)

The DSP Builder MultiwireTranspose block performs a specialized reordering of a block of data and presents it on multiple wires. The size of the block and the number of wires must both be a power of 2.

Each element in the block has a logical address, which DSP Builder forms by concatenating its spatial address (wire number) with its temporal address (slot number). The spatial address is the least-significant part of the logical address; the temporal address is the most significant part.The block specifies the reordering as an arbitrary permutation of the address bits.The block numbers the address bits from 0 (least significant). The block specifies the permutation by listing the address bits in order, starting with the least significant.

For example: specifying:

[7 6 5 4 3 2 1 0] bit-reverses a block of 256 elements

[6 7 4 5 2 3 0 1] digit reverses a block (radix 4)

[0 1 2 3 4 5 6 7] leaves the order of the data unchanged

[6 7 0 1 2 3 4 5] rotates the address bits

[2 3 4 5 6 7 0 1] is be the inverse rotation.

Table 132.  Parameters for the MultiwireTranspose Block
Parameter Description
Address permutation A vector of integers that describes how to rearrange the block of data.
N The number of spatial address bits. The block has 2N data wires.
Table 133.  Port Interface for the MultiwireTranspose Block
Signal Direction Type Description
v Input Boolean. Input valid signal.
d Input Any type. Data input.
qv Output Boolean. Output valid signal.
q Output Same as d Data output.