DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023
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Document Table of Contents
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9.1. ALU Folding

ALU folding generates an ALU architecture specific to the DSP Builder design. The functional units in the generated ALU architecture depend on the blocks and data types in your design. DSP Builder maps the operations performed by connecting blocks in Simulink to the functional units on the generated architecture.

ALU folding reduces the resource consumption of a design by as much as it can while still meeting the latency constraint. The constraint specifies the maximum number of clock cycles a system with folding takes to process a packet. If ALU folding cannot meet this latency constraint, or if ALU folding cannot meet a latency constraint internal to the DSP Builder system due to a feedback loop, you see an error message stating it is not possible to schedule the design.