DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 12/04/2023

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6.13.13. Hello World

This DSP Builder design example produces a simple text message that it stores in a look-up table.

An external input enables a counter that addresses a lookup-table (LUT) that contains some text. The design example writes the result to a MATLAB array. You can examine the contents with a char(message) command in the MATLAB command window.

This design example does not use any ChannelIn, ChannelOut, GPIn, or GPOut blocks. The design example uses Simulink ports for simplicity although they prevent the automatic testbench flow from working.

The top-level testbench includes Control, Signals, Run ModelSim, and Run Quartus Prime blocks.

The Chip subsystem includes Device, Counter, Lut, and SynthesisInfo blocks.

Note: In this design example, the top-level of the FPGA device (marked by the Device block) and the synthesizable Primitive subsystem (marked by the SynthesisInfo block) are at the same level.

The model file is helloWorld.mdl.