External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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6.4.3. Pin Guidelines for Intel® Agilex™ FPGA EMIF IP

The Intel® Agilex™ FPGA contains I/O banks on the top and bottom edges of the device, which can be used by external memory interfaces.

Intel® Agilex™ FPGA I/O banks contain 96 I/O pins. Each bank is divided into two sub-banks with 48 I/O pins in each. Sub-banks are further divided into four I/O lanes, where each I/O lane is a group of twelve I/O ports.

The I/O bank, I/O lane, and pairing pin for every physical I/O pin can be uniquely identified by the following naming convention in the device pin table:

  • The I/O pins in a bank are represented as P#X#Y#, where:
    • P# represents the pin number in a bank. It ranges from P0 to P95, for 96 pins in a bank.
    • X# represents the bank number on a given edge of the device. X0 is the farthest bank from the zipper.
    • Y# represents the top or bottom edge of the device. Y0 and Y1 refer to the I/O banks on the bottom and top edge, respectively.
  • Because an IO96 bank comprises two IO48 sub-banks, all pins with P# value less than 48 (P# <48) belong to the same I/O sub-bank. All other pins belong to the second IO48 sub-bank.
  • The Index Within I/O Bank value falls within one of the following ranges: 0 to 11, 12 to 23, 24 to 35, or 36 to 47, and represents one of I/O lanes 0, 1, 2, or 3, respectively.
  • To determine whether I/O banks are adjacent, you can refer to Figure 2, Figure 3, and , and to the I/O Pin Count Tables located in the Intel® Agilex™ General Purpose I/O and LVDS SERDES User Guide.

    In general, you can assume that I/O banks are adjacent within an I/O edge, unless the I/O bank is not bonded out on the package (indicated by the presence of the " - " symbol in the I/O table), or if the I/O bank does not contain 96 pins, indicating that it is only partially bonded out. If an I/O bank is not fully bonded out in a particular device, it cannot be included within the span of sub-banks for a larger external memory interface. In all cases, you should use the Intel® Quartus® Prime software to verify that your usage can be implemented.

  • The pairing pin for an I/O pin is in the same I/O bank. You can identify the pairing pin by adding 1 to its Index Within I/O Bank number (if it is an even number), or by subtracting 1 from its Index Within I/O Bank number (if it is an odd number).