External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents Skew Matching Guidelines for DIMM Configurations

The guidelines in this topic apply to any DIMM topology, regardless of DIMM type or number of ranks.

Board designers must observe the following guidelines for DDR4 DIMM skew matching:

  • Perform skew matching in time (picoseconds) rather than in actual trace length, to better account for via delays when signals are routed on different layers.
  • Include both package per-pin skew and PCB delay when performing skew matching.
  • Skew (length) matching for the alert signal is not required.

The following table provides skew matching guidelines for DDR4 DIMM topologies.

Table 112.  Skew Matching Guidelines for DDR4 DIMM Topologies
DIMM Skew Matching Rule Length in Time (ps)
Length matching between DQS and CLK -255ps < CLK - DQS < 425ps
Length matching between DQ and DQS within byte -3.5ps < DQ - DQS < 3.5ps
Length matching between DQS and DQS# < 1ps
Length matching between CLK and CLK# < 1ps
Length matching between CLK0 and CLK1 < 8ps
Length matching between CMD/ADDR/CTRL and CLK -20ps < CLK - CMD/ADDR/CTRL < 20ps
Length matching among CMD/ADDR/CTRL within each channel < 20ps
Include package length in skew matching for FPGA device with no migration Required
Include package length in skew matching for FPGA device with migration Not Recommended