External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents Debugging VREFIN Calibration Failure

  1. Ensure that the VCCIO of the failing group is powered up to VCCIO=1.2V at the FPGA side.
  2. Regenerate the EMIF IP with other Initial VREFIN values. It defaults to 68% when using the default FPGA I/O settings.
    Figure 60. Changing the Initial VREFIN Value