External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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6.5.5. Intel® Agilex™ EMIF-Specific Routing Guidelines for Various DDR4 Topologies

This section discusses EMIF-related layout guidelines for Intel® Agilex™ devices.

The Intel® Agilex™ family pin floorplan is a HEX pattern with 1mm pitch. The following figure shows an example of DDR routing for an IO12 (one-byte data) on PCB within FPGA fan-out region.

Figure 99.  Intel® Agilex™ 1mm HEX pin pattern/floorplan and recommended routing for one byte of data (IO12)

The following general notes apply to the EMIF routing guidelines tables in subsequent topics:

  • All spacing requirements are the minimum requirement to be met on PCB in EMIF routing guideline table.
  • Breakout (BO1/BO2) spacings have two different values in guideline tables. The first value represents minimum spacing between two signals routed as a pair (tightly coupled signals), and the second value represents minimum spacing between two pairs.
  • Main route (M) spacings have both value in mil and formula. In formula, h represents the trace-to-nearest-reference-plane height or distance. In cases using a stackup different than the reference stackup, board designers shall use formula to calculate the correct spacing requirements.
  • There is no differential impedance target for CLK nor DQS. Board designers shall follow single-ended impedance target and keep the signals within the pair closely coupled, within 3-4 mil spacing. Board designers can still follow differential impedance target if the trace/space geometry of differential signals fit into FPGA fan out region.
  • In guideline tables, SL stands for stripline routing recommendation and US stands for upper surface (Microstrip) routing recommendation.
  • The trace width value/geometry in guideline tables stands for trace designed for target impedance based on the reference stackup. This trace geometry shall be designed based on actual stackup and target impedance in guideline table.
  • In guideline tables, BO1 and BO2 represent fan-out routing lengths. M stands for out of fan-out (PCB main) routing lengths