External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane

An I/O bank contains two sub-banks. Each sub-bank contains 48 I/O pins, organized into four I/O lanes of 12 pins each. You can identify where a pin is located within an I/O bank based on its Index within I/O Bank in the device pinout.
Table 3.  Pin Index Mapping
Pin Index Lane Sub-bank Location
0-11 0 Bottom
12-23 1
24-35 2
36-47 3
48-59 0 Top
60-71 1
72-83 2
84-95 3

Each I/O lane can implement one x8/x9 read capture group (DQS group), with two pins functioning as the read capture clock/strobe pair (DQS/DQS#), and up to 10 pins functioning as data pins (DQ and DM pins). To implement a x18 group, you can use multiple lanes within the same sub-bank.

It is also possible to implement a pair of x4 groups in a lane. In this case, four pins function as clock/strobe pair, and 8 pins function as data pins. DM is not available for x4 groups. There must be an even number of x4 groups for each interface.

For x4 groups, DQS0 and DQS1 must be placed in the same I/O lane as a pair. Similarly, DQS2 and DQS3 must be paired. In general, DQS(x) and DQS(x+1) must be paired in the same I/O lane.

For DQ and DQS pin assignments for various configurations, refer to the Intel® Agilex™ device pin tables at the following location: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html.

Table 4.  Lanes Used Per DQS Group
Group Size Number of Lanes Used Maximum Number of Data Pins per Group
x8 / x9 1 10
x18 2 22
pair of x4 1 4 per group, 8 per lane
Figure 24. x4 Group

Figure 25. x8 Group

Figure 26. x18 Group

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