External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents Hard Memory Controller Features

Table 9.  Features of the Intel® Agilex™ Hard Memory Controller
Feature Description
Memory standards support

Supports DDR4 SDRAM.

Memory devices support Supports the following memory devices:
  • Discrete
3D Stacked Die support Supports 2 and 4 height of 3D stacked die for DDR4 to increase memory capacity.
Memory controller bypass mode (Future support.) You can use this configurable mode to bypass the hard memory controller and use your own customized controller.
Interface protocols support
  • Supports Avalon® memory-mapped interface.
  • The PHY interface adheres to the AFI protocol.
Rate support The legal options are:
  • HMC half-rate, user logic half-rate (extremely slow interfaces only)
  • HMC half-rate, user-logic quarter-rate
  • HMC quarter-rate, user-logic quarter-rate (extremely high-speed interfaces only)
Configurable memory interface width Supports data widths from 8 to 72 bits, in 8 bit increments
Multiple ranks support Supports:
  • 4 ranks with single slot
  • 2 ranks with dual slots
Burst adapter

Able to accept burst lengths of 1–127 on the local interface of the controller and map the bursts to efficient memory commands. For applications that must strictly adhere to the Avalon® memory-mapped interface specification, the maximum burst length is 64.

No burst chop support for DDR4.

Efficiency optimization features
  • Open-page policy—by default, opens page on every access. However, the controller intelligently closes a row based on incoming traffic, which improves the efficiency of the controller especially for random traffic.
  • Pre-emptive bank management—the controller issues bank management commands early, which ensures that the required row is open when the read or write occurs.
  • Data reordering—the controller reorders read/write commands.
  • Additive latency—the controller can issue a READ/WRITE command after the ACTIVATE command to the memory bank prior to tRCD, which increases the command efficiency.
Starvation counter Ensures all requests are served after a predefined time out period, which ensures that low priority access are not left behind while reordering data for efficiency.
Bank interleaving Able to issue read or write commands continuously to "random" addresses. You must correctly cycle the bank addresses.
On-die termination The controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design.
Refresh features
  • User-controlled refresh timing—optionally, you can control when refreshes occur and this allows you to prevent important read or write operations from clashing with the refresh lock-out time.
  • Per-rank refresh—allows refresh for each individual rank.
  • Controller-controlled refresh.
ECC support
  • 8 bit ECC code; single error correction, double error detection (SECDED).
  • User ECC supporting pass through user ECC bits as part of data bits.
  • ECC is based on a Hamming coding scheme.
Power saving features
  • Low power modes (power down and self-refresh)—optionally, you can request the controller to put the memory into one of the two low power states.
  • Automatic power down—puts the memory device in power down mode when the controller is idle. You can configure the idle waiting time.
  • Memory clock gating.
DDR4 features
  • Bank group support—supports different timing parameters for between bank groups.
  • Command/Address parity—command and address bus parity check.
  • Support Direct Dual CS Mode and Direct QuadCS Mode for DDR4 LRDIMM devices.
  • Support Encoded Quad CSMode for single CS assertion memory mapping for DDR4 LRDIMM devices.
User ZQ calibration Long or short ZQ calibration request for DDR4.