External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents Driver Margining Tab

The Driver Margining feature lets you measure margins on your memory interface using a driver with predefined traffic patterns. Margins measured with this feature are expected to be smaller than margins measured during calibration, because this traffic pattern is longer than those run during calibration, and is intended to stress the interface.

Driver Margining is supported only when a memory interface meets all of the following criteria:

  • Is connected to a TG IP (altera_emif_tg_avl). (That is, it is not using the TG2 configurable traffic generator.)
  • Does not have ECC enabled.
  • Has ISSPs enabled in the project’s QSF file.

To use Driver Margining, press the Run Driver Margining button at the top-left of the tab.

The toolkit then measures margins for DQ read, DQ write, and DM. The process usually takes a few minutes, depending on the margin size, the interface size, and the duration of the driver tests.

The system displays the test results in the table when the test has completed.

Figure 154. Driver Margining Tab

The Driver Margining report can also be viewed in a graphical format. Refer to Viewing Reports Graphically in the Eye Viewer.