External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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4.3.3. AFI Read Sequence Timing Diagrams

The following waveforms illustrate the AFI write data waveform in full and quarter-rate respectively.

The afi_rdata_en_full signal must be asserted for the entire read burst operation. The afi_rdata_en signal need only be asserted for the intended read data.

Aligned and unaligned access for read commands is similar to write commands; however, the afi_rdata_en_full signal must be sent on the same memory clock in a PHY clock as the read command. That is, if a read command is sent on the second memory clock in a PHY clock, afi_rdata_en_full must also be asserted, starting from the second memory clock in a PHY clock.

Figure 81. AFI Read Data Full-Rate

In the following figure, the first three read commands are aligned accesses where they are issued on the LSB of afi_command. The fourth read command is unaligned access, where it is issued on a different command slot. AFI signals must be shifted accordingly, based on command slot.

Figure 83. AFI Read Data Quarter-Rate