External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents QDR-IV Write Calibration

Write Leveling Calibration

The algorithm optimizes the CK versus DK relationship. It is covered by address and command deskew calibration using the loopback mode.

Write Deskew

The algorithm performs per-bit deskew of write data relative to the write strobe and clock. Write deskew calibration does not change dqs_out delays; the write clock is aligned to the CK clock during write leveling.