External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents mem for DDR4

Interface between FPGA and external memory
Table 20.  Interface: memInterface type: Conduit
Port Name Direction Description
mem_ck Output CK clock
mem_ck_n Output CK clock (negative leg)
mem_a Output Address
mem_ba Output Bank address
mem_bg Output Bank group
mem_cke Output Clock enable
mem_cs_n Output Chip select
mem_odt Output On-die termination
mem_reset_n Output Asynchronous reset
mem_act_n Output Activation command
mem_par Output Command and address parity
mem_dq Bidirectional Read/write data
mem_dbi_n Bidirectional Acts as either the data bus inversion pin, or the data mask pin, depending on configuration.
mem_dqs Bidirectional Data strobe
mem_dqs_n Bidirectional Data strobe (negative leg)
mem_alert_n Input Alert flag