External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents Resource Sharing Guidelines (Multiple Interfaces)

In the external memory interface IP, different external memory interfaces can share PLL reference clock pins, core clock networks, I/O banks, and hard Nios® processors. Each I/O bank has DLL and PLL resources, therefore these do not need to be shared. The Intel® Quartus® Prime Fitter automatically merges DLL and PLL resources when a bank is shared by different external memory interfaces, and duplicates them for a multi-I/O-bank external memory interface.

PLL Reference Clock Pin

To conserve pin usage and enable core clock network and I/O bank sharing, you can share a PLL reference clock pin between multiple external memory interfaces; the interfaces must be of the same protocol, rate, and frequency. Sharing of a PLL reference clock pin also implies sharing of the reference clock network.

Observe the following guidelines for sharing the PLL reference clock pin:

  1. To share a PLL reference clock pin, connect the same signal to the pll_ref_clk port of multiple external memory interfaces in the RTL code.
  2. Place related external memory interfaces in the same I/O column.
  3. Place related external memory interfaces in adjacent I/O banks. If you leave an unused I/O bank between the I/O banks used by the external memory interfaces, that I/O bank cannot be used by any other external memory interface with a different PLL reference clock signal.

I/O Bank

To reduce I/O bank utilization, you may share an I/O Bank with other external memory interfaces.

Observe the following guidelines for sharing an I/O Bank:

  1. Related external memory interfaces must have the same protocol, rate, memory clock frequency, and PLL reference clock.
  2. You cannot use a given I/O bank as the address and command bank for more than one external memory interface.
  3. You cannot share an I/O lane between external memory interfaces. Also, any pin in the same bank that is not used by an external memory interface may not be available for use as a general purpose I/O pin.
  4. You cannot share sub-banks between external memory interfaces.