External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

11.9.5.1. Test Duration / Instruction pattern

In the traffic generator, a loop refers to a set of writes followed by a set of reads.

Example test pattern:

TG_LOOP_COUNT=2     TG_WRITE_REPEAT_COUNT=1     TG_RW_GEN_IDLE_COUNT=0
TG_WRITE_COUNT=3     TG_READ_REPEAT_COUNT=1     TG_RW_GEN_LOOP_IDLE_COUNT=4
TG_READ_COUNT=3     TG_BURST_LENGTH=2
Figure 167. Timing Diagram for Example Test Pattern