External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 1/31/2022

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Document Table of Contents ctrl_mmr_slave for DDR4

Controller MMR slave interface
Table 35.  Interface: ctrl_mmr_slaveInterface type: Avalon Memory-Mapped Slave
Port Name Direction Description
mmr_slave_waitrequest Output Wait-request is asserted when controller MMR interface is busy
mmr_slave_read Input MMR read request signal
mmr_slave_write Input MMR write request signal
mmr_slave_address Input Word address for MMR interface of memory controller
mmr_slave_readdata Output MMR read data
mmr_slave_writedata Input MMR write data
mmr_slave_burstcount Input Number of transfers in each read/write burst
mmr_slave_beginbursttransfer Input Indicates when a burst is starting
mmr_slave_readdatavalid Output Indicates whether MMR read data is valid